1. Field of the Invention
The present invention relates to a continuous conduction mode (CCM) boost voltage power factor correction apparatus with an average current control mode. In particular, a power factor correction apparatus and a method utilizing a resettable integrator to achieve high power factor and low total harmonic distortion (THD) for an electrical power system.
2. Description of the Related Art
A high quality electrical power supply is a desired goal for every country in the world. However, building a lot of electrical power plants is not the only way to achieve the goal. For achieving the goal effectively, on the one hand a country can increase their electrical power supply, on the other hand they can also improve the power factor or the efficiency of electrical appliances.
A power factor correction (PFC) is used for making the input voltage of an electrical appliance in phase with the input current. Therefore, PFC makes the loading of the electrical appliance resistive to the electrical power system hence improving the energy efficiency.
PFC circuits are divided into discontinuous conduction mode power factor correction (DCM PFC) and continuous conduction mode power factor correction (CCM PFC). FIG. 1 shows the circuit diagram of the discontinuous conduction mode power factor correction with a peak current control mode of the prior art. The discontinuous conduction mode power factor correction (DCM PFC) 101 adopts a peak current control mode. When an alternating current (AC) is inputted, the peak current control mode rectifies the voltage into a voltage shape that is similar to an m-shaped via a bridge rectifier 10. The voltage is divided by two resistors R5 and R6. Next, the divided voltage is multiplied by an output signal VC that is amplified by an error amplifier via a multiplier 14 to obtain an output voltage Vm that is similar to m-shaped. The above circuit provides a reference voltage Vm for the peak current that flows through a detection resistor Rs. The reference voltage Vm is adjusted according to the input voltage and the output voltage.
The output voltage Vout is divided by the resistors R3 and R4 and is negatively fed back to the input port of the multiplier 14 via an error amplifier 12. By the above method, the output voltage Vout remains on a fixed level while the loading is changing. The output voltage Vm is connected to the positive input port of a comparator 16 and compared with a voltage Vs (the voltage drop produced by flowing the current of transistor Q through the detection resistor Rs) connected at the negative input port to control the transistor Q turn on). The discontinuous conduction mode power factor correction (DCM PFC) 101 utilizes a zero current crossing detector 13 to achieve the zero current for turn off of the transistor Q.
FIG. 2 shows a schematic diagram of waveforms of each point of the circuit of the FIG. 1. The waveform includes the voltage Vs between two ends of the detection resistor Rs, the inductor current iL on the inductor L, and a gate voltage Vgate for controlling whether the transistor Q is on or off. The phase of the average current iL that flows through the inductor L is the same as the phase of the output voltage Vm of the multiplier 14. Thereby, the power factor is amended. The major drawback of DCM PFC is its high THD due to large ripple current.
FIG. 3 shows a circuit diagram of the continuous conduction mode power factor correction with an average current control mode of the prior art. The shown continuous conduction mode power factor correction (CCM PFC) 1001 adopts an average current control mode. An alternating current (AC) is inputted and is rectified into an input voltage Vin that is similar to the m-shaped via a bridge rectifier 10. A multiplier 20 has an input signal A of the output voltage Vout via a voltage amplifier 24, an input signal B from the input voltage Vin via a preset circuit 22, and a square signal C2 of the average value of the input voltage Vin. The multiplier 20 processes the multiplication operation between the amplified signal A and the input signal B and divides it by the square signal C2 to obtain a current command signal VP that is similar to an m-shaped. The operation of dividing by the square signal C2 prevents the power factor of the power factor correction from changing with the magnitude of the input signal B received from the input voltage Vin. The amplifying signal A is used for controlling the switch of the transistor Q via a control circuit to make the voltage stable even though the output voltage is changing.
FIG. 4 shows a schematic diagram of waveforms of each point of the circuit of the FIG. 3. The gate driving pulse GS is the result of comparing the triangle waveform VS and the command signal Vc. The duty cycle of the gate driving pulse GS is widest near the wave valley of the command signal Vc and is narrowest near the wave peak of the command signal Vc. In the FIG. 4, the current waveform iL of the inductor L is obtained by controlling the transistor Q via the gate driving pulse GS. The current waveform iL flows through a capacitor Cin located at the input port and is filtered to obtain a current waveform iL (avg) that is similar to a sine wave. The current waveform iL (avg) that is similar to a sine wave has the same phase with the input voltage Vin. Thereby, the power factor is amended. The power factor correction having a multiplier needs a lot of components and its design is complex. It is difficult to design a single chip because of the large number of components and pin numbers needed for the chip.